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A Reconfigurable Pipelined ADC in 0.18 um CMOS

Författare:
Publiceringsår: 2005
Språk: Engelska
Sidor: 326-329
Publikation/Tidskrift/Serie: 2005 Symposium on VLSI Circuits, Digest of Technical Papers
Dokumenttyp: Konferensbidrag
Förlag: IEEE Press

Sammanfattning

A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Symposium on VLSI Circuits
2014-06-17
Kyoto, Japan
Published
Yes
  • ISBN: 4-900784-01-X

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