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A 8-bit 100-MHz CMOS linear interpolation DAC

Författare:
Publiceringsår: 2003
Språk: Engelska
Sidor: 1758-1761
Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
Volym: 38
Nummer: 10
Dokumenttyp: Artikel
Förlag: IEEE

Sammanfattning

An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.

Disputation

Nyckelord

  • Technology and Engineering

Övrigt

Published
Yes
  • ISSN: 0018-9200

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