A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
Publikation/Tidskrift/Serie: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.
This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption
- Electrical Engineering, Electronic Engineering, Information Engineering
30 May-2 June 1999
- ISBN: 0-7803-5471-0