Du är här

A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing

Författare:
Publiceringsår: 2008
Språk: Engelska
Sidor: 398-404
Dokumenttyp: Konferensbidrag
Förlag: IEEE Press

Sammanfattning

This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

IEEE International Symposium on Electronic Design, Test & Applications (DELTA)
2008-01-23/2008-01-25
Hong Kong
Published
Yes
  • Digital ASIC
"©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."
  • ISBN: 978-0-7695-3110-6

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

 

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen