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A parallel 2Gops/s image convolution processor with low I/O bandwidth

Författare:
Publiceringsår: 1995
Språk: Engelska
Sidor: 87-90
Dokumenttyp: Konferensbidrag

Sammanfattning

A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

IEEE ASIC Conference and Exhibit
1995-09-18/1995-09-22
Austin, TX, USA
Published
Yes
"©1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."
  • ISSN: 1063-0988
  • ISBN: 0-7803-2707-1

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