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Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding

Författare:
Publiceringsår: 2010
Språk: Engelska
Sidor: 347-356
Publikation/Tidskrift/Serie: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation
Volym: 5953
Dokumenttyp: Konferensbidrag
Förlag: Springer

Sammanfattning

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency the sub-threshold (sub-VT ) domain. The design is synthesized in 65nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.

Disputation

Nyckelord

  • Technology and Engineering
  • folding
  • energy model
  • sub-threshold
  • QRS detection
  • Cardiac pacemaker
  • wavelet filterbank
  • time-multiplexing

Övriga

19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009
2009-09-9/11
Delft, The Netherlands
  • Vetenskapsrådet
Published
  • Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
Yes
  • Elektronikkonstruktion
  • Digital ASIC
  • ISSN: 0302-9743

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