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Bit-Serial CORDIC: Architecture and Implementation Improvements

In English

Författare

  • Johan Löfgren
  • Peter Nilsson

Summary, in English

Abstract in Undetermined
This paper presents a new and improved bit-serial CORDIC architecture. A detailed description of the bit-serial implementation and its Control Unit is presented. It is shown that the improvement is due to a reduction of registers in the implementation and is made possible by ensuring that the angular path is calculated prior to the corresponding vector paths. In addition, the improved architecture is implemented in VHDL and synthesized for a UMC 130 nm technology. With the chosen parameters, a word length of 12 bits and 8 stages in the CORDIC, it is shown that the improved architecture is 20 % smaller and consumes 26 % less power.

Publiceringsår

2010

Språk

Engelska

Sidor

65-68

Publikation/Tidskrift/Serie

Midwest Symposium on Circuits and Systems Conference Proceedings

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

2010 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010)

Conference date

2010-08-01

Conference place

Seattle, Washington, United States

Status

Published

Forskningsgrupp

  • Digital ASIC

ISBN/ISSN/Övrigt

  • ISSN: 1558-3899
  • ISSN: 1548-3746
  • ISBN: 978-1-4244-7773-9