Meny

Javascript is not activated in your browser. This website needs javascript activated to work properly.
Du är här

A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver

Författare:
Publiceringsår: 2005
Språk: Kinesiska
Sidor: 1641-1645
Publikation/Tidskrift/Serie: Journal of Semiconductors
Volym: 26
Nummer: 8
Dokumenttyp: Artikel

Sammanfattning

A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS technology and a power supply of 3.3v.

Disputation

Nyckelord

  • Technology and Engineering
  • Ethernet frequency synthesizer clock jitter

Övriga

Published
Yes
  • ISSN: 1674-4926

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen