Hardware architecture for matrix factorization in MIMO receivers
Publikation/Tidskrift/Serie: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI
This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations.
- Electrical Engineering, Electronic Engineering, Information Engineering
The 17th ACM Great Lakes Symposium on VLSI (GLSVLSI)
- ISBN: 978-1-59593-605-9