Meny

Javascript is not activated in your browser. This website needs javascript activated to work properly.
Du är här

High speed CMOS circuit technique

Författare:
Publiceringsår: 1989
Språk: Engelska
Sidor: 62-70
Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
Volym: 24
Nummer: 1
Dokumenttyp: Artikel
Ytterligare information: IEEE Solid-State Circuits Council 1988-89 Best Paper Award

Sammanfattning

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Published
Yes
  • ISSN: 0018-9200

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen