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High speed CMOS circuit technique

In English

Författare

  • Jiren Yuan
  • Christer Svensson

Summary, in English

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz

Publiceringsår

1989

Språk

Engelska

Sidor

62-70

Publikation/Tidskrift/Serie

IEEE Journal of Solid-State Circuits

Volym

24

Issue

1

Dokumenttyp

Artikel i tidskrift

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Övrigt

  • ISSN: 0018-9200