CMOS circuit speed optimization based on switch level simulation

In English The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.