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A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter

Författare:
Publiceringsår: 2012
Språk: Engelska
Sidor:
Dokumenttyp: Konferensbidrag

Sammanfattning

Two branches of gated ring oscillators (GRO)

act as the delay lines in 2-dimension Vernier

time-to-digital converter (TDC). The proposed

architecture reduces dramatically the inherent latency of

vernier structure. The already small quantization noise of

the standard Vernier TDC is further first-order shaped by

the GRO operation. The TDC has been simulated in 90nm

CMOS technology. Operating from 50MHz reference

frequency, it achieves a resolution better than 2ps

assuming a signal bandwidth of 1.56MHz (OSR=16), for a

minimum current consumption of 1.8mA from 1.2V.

Nyckelord

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Digitall PLL
  • TDC
  • GRO
  • 2-dimention

Övriga

Norchip conference, 2012
Inpress
  • Analog RF-lup-obsolete

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu.se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
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