Publikationer
Power Constrained Test Scheduling for 3D Stacked Chips : (poster)
Avdelning/ar:
Publiceringsår: 2010
Språk: Engelska
Dokumenttyp: Konferensbidrag
Sammanfattning
Disputation
Nyckelord
- Technology and Engineering
Övrigt
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
Austin, TX, USA
Published
Yes
