Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Författare
Summary, in English
Publiceringsår
2008
Språk
Engelska
Sidor
188-193
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- testing
- system-on-chip
- test-architecture optimization
- test scheduling
- test patterns
- compression
- test access mechanism
- TAM
- SOC
Conference name
Design, Automation, and Test in Europe DATE 2008
Conference date
2008-03-10 - 2008-03-14
Conference place
Munich, Germany
Status
Published
ISBN/ISSN/Övrigt
- ISBN: 978-3-9810801-3-