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Optimized Integration of Test Compression and Sharing for SOC Testing

Författare:
Publiceringsår: 2007
Språk: Engelska
Sidor:
Dokumenttyp: Konferensbidrag
Förlag: IEEE Computer Society Press

Sammanfattning

The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.

Disputation

Nyckelord

  • Technology and Engineering
  • testing
  • system-on-chip
  • SOC
  • test scheduling
  • memory requirements
  • test data compression
  • constraint logic programming

Övriga

Design, Automation, and Test in Europe Conference DATE07
2007-04-16/2007-04-20
Nice, France
Published
Yes
  • ISBN: 978-3-9810801-2-4

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