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A Digital PLL with a Multi-Delay Coarse-Fine TDC

Författare:
Publiceringsår: 2011
Språk: Engelska
Sidor: 4
Dokumenttyp: Konferensbidrag

Sammanfattning

A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implement-ed. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Norchip
2011-11-16
Lund, Sweden
Published
Yes
  • ISBN: 978-1-4577-0514-4

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