Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
Förlag: IEEE Computer Society
In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measure- ment and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.
- Electrical Engineering, Electronic Engineering, Information Engineering
- Test Scheduling
- IEEE P1687
Test Symposium (ATS), 2011 20th Asian
New Delhi, India
- Digital ASIC
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- ISSN: 1081-7735
- ISBN: 978-1-4577-1984-4