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Silent CMOS circuits aiming for system-on-chip

Publiceringsår: 2005
Språk: Engelska
Sidor: 278-281
Publikation/Tidskrift/Serie: 2005 6th International Conference on ASIC Proceedings
Volym: 1
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


A silent CMOS circuit architecture is proposed. Different silent CMOS gate solutions are presented and compared to the normal CMOS precharged gate in switching noise level. A silent 16-bit parallel carry-look-ahead adder is demonstrated. Simulation results on the circuits and the post layout of the adder are given, which shows a 10 times reduction in noise level is possible


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • 16 bit
  • parallel carry look ahead adder
  • switching noise
  • system-on-chip
  • silent CMOS circuit architecture
  • noise level reduction


2005 6th International Conference on ASIC Proceedings
  • ISBN: 0780392108
  • ISBN: 0-7803-9210-8

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