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A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations

  • Mattias Andersson
  • Martin Andersson (Assistant Professor)
  • Lars Sundström
  • Pietro Andreani
Publiceringsår: 2012
Språk: Engelska
Sidor: 245-248
Publikation/Tidskrift/Serie: IEEE Asian Solid State Circuits Conference (A-SSCC), 2012
Dokumenttyp: Konferensbidrag
Förlag: IEEE


This paper presents a 3rd-order, 3-bit continuous time (CT) Delta-Sigma modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65nm CMOS process, where it occupies an area of 0.2mmx0.4mm. It achieves an SNR of 71dB and an SNDR of 69dB over a 9MHz bandwidth with an oversampling ratio of 16. Power consumption is 7.5mW from a 1.2V supply, for a figure-of-merit of 181fJ/conversion.



  • Electrical Engineering, Electronic Engineering, Information Engineering


IEEE Asian Solid-State Circuits Conference (ASSCC)
Kobe, Japan
  • EIT_DRAGON Digital Radio Architectures Going Nanoscale
  • Data converters & RF
  • ISBN: 978-1-4673-2468-8

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