Digital background calibration in continuous-time delta-sigma analog to digital converters

Summary, in English

This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.

• Författare: Siyu Tan; Yun Miao; Mattias Andersson; Joachim Rodrigues; Piero Andreani
• Avdelning/ar: Institutionen för elektro- och informationsteknik; System på chips (master); ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2015
• Språk: Engelska
• Publikation/Tidskrift/Serie: Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
• Länkar: http://dx.doi.org/10.1109/NORCHIP.2015.7364377
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: Delta-Sigma; Digital calibration
• Conference name: Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
• Conference date: 2015-10-26 - 2015-10-28
• Conference place: Oslo, Norway
• Status: Published