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Scenario-Based Network Design for P1687

In English

Författare

Summary, in English

To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead.

Publiceringsår

2013

Språk

Engelska

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • IEEE P1687 (IJTAG)
  • on-chip instruments
  • access time
  • test time
  • ICL
  • network design

Conference name

Swedish System-On-Chip Conference (SSoCC), 2013

Conference date

2013-05-06 - 2013-05-07

Conference place

Ystad, Sweden

Status

Published

Forskningsgrupp

  • Digital ASIC