A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
Författare
Summary, in English
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.
Publiceringsår
2015
Språk
Engelska
Publikation/Tidskrift/Serie
2014 NORCHIP
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
32nd NORCHIP Conference, 2014
Conference date
2014-10-27 - 2014-10-28
Conference place
Tampere, Finland
Status
Published
ISBN/ISSN/Övrigt
- ISBN: 978-1-4799-5442-1