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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

In English

Författare

Summary, in English

Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.

Publiceringsår

2016-08-08

Språk

Engelska

Sidor

966-969

Publikation/Tidskrift/Serie

IEEE Electron Device Letters

Volym

37

Issue

8

Dokumenttyp

Artikel i tidskrift

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • vertical
  • nanowire
  • InAs
  • MOSFET
  • transistor
  • gate-last
  • self-aligned

Status

Published

Forskningsgrupp

  • Nano Electronics

ISBN/ISSN/Övrigt

  • ISSN: 0741-3106