Implementation of a Scalable Matrix Inversion Architecture for Triangular Matrices

In English This paper presents an FPGA implementation of a
novel snd Ihighl! scalable hardware architecture for inversion of triangiiliir matrices. An integral part of modern signal processing and communications applications involves manipulation of large matrices. Therefore, scalable and flexible hardware architectures
are increasingly sought for. In this paper the traditional
triangular shaped array architecture with n(n+l)/Z, where n
being the number of inputs, communicating processors are
mapped to a linear structure with only n processors. We show that the linear array structure avoids drawbacks such as nonscalability, large area and large power consumption. The implementation is based on a numerical stable recurrence algorithm which has excellent properties for hardware implementation. The implementation is the core processor in a smart antenna system.