Du är här

Implementation of a Scalable Matrix Inversion Architecture for Triangular Matrices

Publiceringsår: 2003
Språk: Engelska
Sidor: 2558-2562
Volym: 3
Dokumenttyp: Konferensbidrag

Sammanfattning

This paper presents an FPGA implementation of a
novel snd Ihighl! scalable hardware architecture for inversion of triangiiliir matrices. An integral part of modern signal processing and communications applications involves manipulation of large matrices. Therefore, scalable and flexible hardware architectures
are increasingly sought for. In this paper the traditional
triangular shaped array architecture with n(n+l)/Z, where n
being the number of inputs, communicating processors are
mapped to a linear structure with only n processors. We show that the linear array structure avoids drawbacks such as nonscalability, large area and large power consumption. The implementation is based on a numerical stable recurrence algorithm which has excellent properties for hardware implementation. The implementation is the core processor in a smart antenna system.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Personal, Indoor and Mobile Radio Communications (PIMRC)
Beijing, China
Published
Yes

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

 

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen