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Balancing BlockRAM and distributed RAM

Författare:
Publiceringsår: 2005
Språk: Engelska
Publikation/Tidskrift/Serie: Proceedings SSoCC 2005
Dokumenttyp: Konferensbidrag

Sammanfattning

Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

Disputation

Nyckelord

  • Technology and Engineering

Övrigt

Swedish System-on-Chip Conference (SSoCC)
Tammsvik
Published
Yes

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