Balancing BlockRAM and distributed RAM

In English Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.