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A VLSI architecture of the Schnorr-Euchner decoder for MIMO systems

Publiceringsår: 2004
Språk: Engelska
Sidor: 65-68
Publikation/Tidskrift/Serie: Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
Volym: 1
Dokumenttyp: Konferensbidrag
Förlag: Institute of Electrical and Electronics Engineers Inc

Sammanfattning

The lattice decoder is shown to approach the performance of Maximum-likelihood decoder for MIMO wireless systems with low complexity. A VLSI architecture of the K-best Schnorr-Euchner lattice decoder is proposed in this paper. The architecture is optimized on both algorithm and architecture levels, and supports a dynamic range of SNR [less-than or equal to] 30 dB. Compared to a conventional VLSI implementation of the lattice decoder for MIMO systems, the proposed architecture results in up to 37% computation reductions, 20% area savings and more than 5 times decoding throughput improvements. The proposed architecture is implemented with 0.35 μm technology for a system of 4 transmit/receive antennas and 16-QAM modulation. The results show that a decoding throughput of 53.3 Mbits/s can be achieved, and the decoding latency is less than 2.5 μs. © 2004 IEEE.

Disputation

Nyckelord

  • Technology and Engineering
  • MIMO
  • Packet error rates (PER)
  • Schnorr-Euchner decoder
  • Sphere decoders

Övriga

Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
May 31-Jun 2 2004
Shanghai, China
Published
Yes
  • Elektronikkonstruktion
  • ISBN: 0780379381

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