Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS

Summary, in English

Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.

• Författare: Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg; Joachim Rodrigues
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2013
• Språk: Engelska
• Sidor: 192-200
• Publikation/Tidskrift/Serie: Proceedings of the ESSCIRC (ESSCIRC), 2013
• Länkar: http://dx.doi.org/10.1109/ESSCIRC.2013.6649106
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE European Solid State Circuits Conference, ESSCIRC 2013
• Conference date: 2013-09-16 - 2013-09-20
• Conference place: Bucharest, Romania
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 1930-8833; ISBN: 978-1-4799-0643-7