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A digitally controlled PLL for digital SOCs

In English

Författare

  • Thomas Olsson
  • Peter Nilsson

Summary, in English

A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.

Publiceringsår

2003

Språk

Engelska

Sidor

437-440

Publikation/Tidskrift/Serie

Proceedings - IEEE International Symposium on Circuits and Systems

Volym

5

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • Digital systems

Conference name

Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Conference date

2003-05-25 - 2003-05-28

Conference place

Bangkok, Thailand

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion

ISBN/ISSN/Övrigt

  • ISSN: 2158-1525
  • ISSN: 0271-4310
  • CODEN: PICSDI