Optimal System-on-Chip Test Scheduling
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test scheduling
- test access mechanisms
- test conflicts
- test wrappers
- TAM routing
12th IEEE Asian Test Symposium ATS03
- ISSN: 1081-7735
- ISBN: 0-7695-1951-2