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New domino logic precharged by clock and data

Publiceringsår: 1993
Språk: Engelska
Sidor: 2188-2189
Publikation/Tidskrift/Serie: Electronics Letters
Volym: 29
Nummer: 25
Dokumenttyp: Artikel i tidskrift
Förlag: IEE


A clock-and-data precharged dynamic (CDPD) circuit technique in CMOS is presented. It gives a fast one-clock-cycle decision to multilevel logic and has small clock loads, low peak current, small area and low power-delay product. The technique is highly flexible in logic design. For the given example, a 324bit binary-lookahead-carry chain, the speed improvement can be as high as 40–50% compared to the static circuit and 30% to the normal domino circuit arrangements while the area is reduced by 15–30%.


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • ISSN: 1350-911X

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