SOC Test Time Minimization Under Multiple Constraints
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test scheduling
- power limitations
- test conflicts
- test access mechanisms
12th IEEE Asian Test Symposium ATS 2003
- ISSN: 1081-7735
- ISBN: 0-7695-1951-2