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Scheduling Tests for Stacked 3D Chips under Power Constraints

Författare:
Publiceringsår: 2010
Språk: Engelska
Sidor:
Dokumenttyp: Konferensbidrag

Sammanfattning

This paper addresses test application time (TAT)

reduction for core-based stacked 3D chips. In contrast to the

traditional method of testing non-stacked chips where the same

test schedule is applied both at wafer test and at final test, stacked

3D chips need a pre-bond test schedule for each individual chip

and a different post-bond test schedule where all chips are jointly

tested. We consider a system of core-based chips where each core

is tested with a dedicated Built-In Self-Test (BIST) engine and

define an algorithm that defines each pre-bond test schedule and

the post-bond test schedule such that the overall TAT is

minimized and power constraints are met. The cost due to the

number of BIST control-lines is also taken into account.

Experiments with the proposed algorithm show significant savings

in TAT.

Nyckelord

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Built in Self Test (BIST)
  • Design for Test (DfT)
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).

Övriga

Swedish SoC Conference 2010
Published
  • Digital ASIC-lup-obsolete

Box 117, 221 00 LUND
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Telefax 046-222 47 20
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