A continuous-time delta-sigma ADC with integrated digital background calibration

Summary, in English

This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

• Författare: Siyu Tan; Yun Miao; Mattias Palm; Joachim Neves Rodrigues; Pietro Andreani
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2016-11-01
• Språk: Engelska
• Sidor: 273-282
• Publikation/Tidskrift/Serie: Analog Integrated Circuits and Signal Processing
• Volym: 89
• Issue: 2
• Länkar: http://dx.doi.org/10.1007/s10470-016-0800-7
• Dokumenttyp: Artikel i tidskrift
• Förlag: Springer
• Ämne: Signal Processing
• Nyckelord: Background calibration; Continuous-time; Delta-sigma modulator; Digital calibration
• Aktiv: Published
• ISBN/ISSN/Övrigt: ISSN: 0925-1030