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Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS

In English

Författare

  • Peter Nilsson

Summary, in English

The power consumption is becoming a major obstacle in future circuit design. Referring to Moore's law, by adding more functionality in an exponential way, we will also increase the total power consumption in the same pace. VLSI design has traditionally been concerning the dynamic power consumption as the limiting factor in low power system design. Today, when the feature sizes are in the nano-meter scale, the static power consumption is becoming a dominating factor. This paper indicates an arithmetic reduction of the static power consumption down to 20 % by using bit-serial arithmetic instead of bit-parallel.

Publiceringsår

2006

Språk

Engelska

Sidor

656-659

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE 13th International Conference on Electronics, Circuits and Systems (ICECS 2006)

Conference date

2006-12-10 - 2006-12-13

Conference place

Nice, France

Aktiv

Published

Forskningsgrupp

  • Elektronikkonstruktion