Optimized Integration of Test Compression and Sharing for SOC Testing
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test scheduling
- memory requirements
- test data compression
- constraint logic programming
Design, Automation, and Test in Europe Conference DATE07
- ISBN: 978-3-9810801-2-4