Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method
Författare
Summary, in English
The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.
Publiceringsår
2013
Språk
Engelska
Sidor
53-56
Publikation/Tidskrift/Serie
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
43rd Conference on European Solid-State Device Research
Conference date
2013-09-16 - 2013-09-20
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1930-8876