Survivor path processing in Viterbi decoders using register exchange and traceforward
Författare
Summary, in English
This paper proposes a new class of hybrid VLSI
architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and trace-forward algorithms, that is, low memory requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture
can be efficiently applied to codes with a larger number
of states where usually trace-back-based architectures, which increase latency, are dominant.
architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and trace-forward algorithms, that is, low memory requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture
can be efficiently applied to codes with a larger number
of states where usually trace-back-based architectures, which increase latency, are dominant.
Publiceringsår
2007
Språk
Engelska
Sidor
537-541
Publikation/Tidskrift/Serie
IEEE Transactions on Circuits and Systems II: Express Briefs
Volym
54
Issue
6
Fulltext
- Available as PDF - 134 kB
- Download statistics
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- (TB)
- traceback
- survivor path
- convolutional codes
- register exchange (RE)
- traceforward (TF)
- Viterbi decoder
- VLSI
Status
Published
Projekt
- Digital ASIC: Flexible Coding and Decoding for Wireless Personal Area Networks
ISBN/ISSN/Övrigt
- ISSN: 1549-7747