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A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility

Publiceringsår: 2008
Språk: Engelska
Sidor: 137-141
Publikation/Tidskrift/Serie: Proceedings, Norchip Conference
Dokumenttyp: Konferensbidrag


This paper discusses design and measurements of

a flexible Viterbi decoder fabricated in 130-nm digital CMOS.

Flexibility was incorporated by providing various code rates and

modulation schemes to adjust to varying channel conditions.

Based on previous trade-off studies, flexible building blocks were

carefully designed to cause as little area penalty as possible. The

chip runs down to a minimal core supply of 0.8V. It turns out that

striving for more modulation schemes is beneficial in terms of

power consumption once the price is paid for accepting different

code rates viz. radices in the trellis and survivor path units.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Viterbi decoder
  • CMOS
  • flexible chips
  • integrated circuits


Norchip Conference, 2008
  • EIT_HSWC:Coding Coding, modulation, security and their implementation
  • Informations- och kommunikationsteori-lup-obsolete
  • Digital ASIC-lup-obsolete
  • Telecommunication Theory-lup-obsolete

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