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NoC-based CSP support for a Java chip multiprocessor

Publiceringsår: 2010
Språk: Engelska
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.


  • Computer Science
  • NoC
  • CSP
  • multiprocessor
  • Java


NORCHIP Conference, 2010
  • ESDLAB-lup-obsolete
  • ISBN: 978-1-4244-8972-5

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