Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

A low-complexity method for distributed clocking on digital ASICs

In English

Författare

  • Thomas Olsson
  • Peter Nilsson

Summary, in English

A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies

Publiceringsår

2004

Språk

Engelska

Sidor

344-347

Publikation/Tidskrift/Serie

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • local clock generator
  • divider
  • FFT coprocessor
  • unsynchronized clocks
  • digital ASIC
  • synchronous wrappers
  • distributed clocking
  • low-complexity method
  • CMOS technology
  • post-synthesis simulation
  • VHDL-code
  • large SoC
  • 1.8 V

Conference name

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference date

2004-08-04 - 2004-08-05

Conference place

Fukuoka, Japan

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion

ISBN/ISSN/Övrigt

  • ISBN: 0-7803-8637-X