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Design of highly-parallel, 2.2Gbps throughput signal detector for MIMO systems

Publiceringsår: 2008
Språk: Engelska
Sidor: 742-745
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.


  • Electrical Engineering, Electronic Engineering, Information Engineering


IEEE International Conference on Communications ICC 2008
  • ISBN: 978-1-4244-2075-9

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