Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

A hardware efficiency analysis for simplified trellis decoding blocks

In English

Författare

Summary, in English

Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.

Publiceringsår

2005

Språk

Engelska

Sidor

128-132

Publikation/Tidskrift/Serie

[Host publication title missing]

Volym

2005

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • Trellis decoding blocks
  • Computational operations
  • Hardware efficiency

Conference name

IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)

Conference date

2005-11-02 - 2005-11-04

Conference place

Athens, Greece

Status

Published

ISBN/ISSN/Övrigt

  • ISSN: 1520-6130
  • ISBN: 0-7803-9333-3