Defect-Aware SOC Test Scheduling
Publikation/Tidskrift/Serie: VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test scheduling
- sequential scheduling
- concurrent scheduling
- defect probabilities
2004 IEEE VLSI Test Symposium VTS04
- ISSN: 1093-0167
- ISBN: 0-7695-2134-7