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Efficient CMOS counter circuits

  • Jiren Yuan
Publiceringsår: 1988
Språk: Engelska
Sidor: 1311-1313
Publikation/Tidskrift/Serie: Electronics Letters
Volym: 24
Nummer: 21
Dokumenttyp: Artikel i tidskrift
Förlag: IEE


Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • ISSN: 1350-911X

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