Efficient CMOS counter circuits
Författare
Summary, in English
Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal
Publiceringsår
1988
Språk
Engelska
Sidor
1311-1313
Publikation/Tidskrift/Serie
Electronics Letters
Volym
24
Issue
21
Länkar
Dokumenttyp
Artikel i tidskrift
Förlag
IEE
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1350-911X