Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A Reconfigurable Pipelined ADC in 0.18 um CMOS

  • Martin Andersson
  • Karl Norling
  • Andreas Dreyfert
  • Jiren Yuan
Publiceringsår: 2005
Språk: Engelska
Sidor: 326-329
Publikation/Tidskrift/Serie: 2005 Symposium on VLSI Circuits, Digest of Technical Papers
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.


  • Electrical Engineering, Electronic Engineering, Information Engineering


Symposium on VLSI Circuits
  • ISBN: 4-900784-01-X

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen