A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
Författare
Summary, in English
Avdelning/ar
Publiceringsår
2013
Språk
Engelska
Sidor
380-385
Publikation/Tidskrift/Serie
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
Conference date
2013-10-07 - 2013-10-09
Status
Published