A VLSI architecture of the Schnorr-Euchner decoder for MIMO systems

Summary, in English

The lattice decoder is shown to approach the performance of Maximum-likelihood decoder for MIMO wireless systems with low complexity. A VLSI architecture of the K-best Schnorr-Euchner lattice decoder is proposed in this paper. The architecture is optimized on both algorithm and architecture levels, and supports a dynamic range of SNR [less-than or equal to] 30 dB. Compared to a conventional VLSI implementation of the lattice decoder for MIMO systems, the proposed architecture results in up to 37% computation reductions, 20% area savings and more than 5 times decoding throughput improvements. The proposed architecture is implemented with 0.35 μm technology for a system of 4 transmit/receive antennas and 16-QAM modulation. The results show that a decoding throughput of 53.3 Mbits/s can be achieved, and the decoding latency is less than 2.5 μs. © 2004 IEEE.

• Författare: Zhan Guo; Peter Nilsson
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2004
• Språk: Engelska
• Sidor: 65-68
• Publikation/Tidskrift/Serie: Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
• Volym: 1
• Länkar: http://dx.doi.org/10.1109/CASSET.2004.1322918
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: MIMO; Packet error rates (PER); Schnorr-Euchner decoder; Sphere decoders
• Conference name: Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
• Conference date: 2004-05-31 - 2004-06-02
• Conference place: Shanghai, China
• Status: Published
• Forskningsgrupp: Elektronikkonstruktion
• ISBN/ISSN/Övrigt: ISBN: 0780379381