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Multiple Constraints Driven System-on-Chip Test Time Optimization

Publiceringsår: 2005
Språk: Engelska
Sidor: 599-611
Publikation/Tidskrift/Serie: Journal of Electronic Testing
Volym: 21
Nummer: 6
Dokumenttyp: Artikel i tidskrift
Förlag: Springer


The cost oftesting SOCs (systems-on-chip) is highly related to the testapplication time. The problem is that the test application timeincreases as the technology makes it possible to design highlycomplex chips. These complex chips include a high number of faultsites, which need a high test data volume for testing, and the hightest data volume leads to long test application times. For modularcore-based SOCs where each module has its distinct tests,concurrent application of the tests can reduce the test applicationtime dramatically, as compared to sequential application. However,when concurrent testing is used, resource conflicts and constraintsmust be considered. In this paper, we propose a test schedulingtechnique with the objective to minimize the test application timewhile considering multiple conflicts. The conflicts we areconsidering are due to cross-core testing (testing ofinterconnections between cores), module testing with multiple testsets, hierarchical conflicts in SOCs where cores are embedded incores, the sharing of the TAM (test access mechanism), test powerlimitations, and precedence conflicts where the order in whichtests are applied is important. These conflicts must be consideredin order to design a test schedule that can be used in practice. Inparticular, the limitation on the test power consumption isimportant to consider since exceeding the system's power limitmight damage the system. We have implemented a technique tointegrate the wrapper design algorithm with the test schedulingalgorithm, while taking into account all the above constraints.Extensive experiments on the ITC'02 benchmarks show that eventhough we consider a high number of constraints, our techniqueproduces results that are in the range of results produced betechniques where the constraints are not taken intoaccount.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • testing
  • system-on-chip
  • test access mechanism
  • TAM
  • test optimization


  • ISSN: 0923-8174

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