A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's

Summary, in English

This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage

• Författare: Peter Nilsson; Mats Torkelson
• Avdelning/ar: Institutionen för elektro- och informationsteknik; Institutioner vid LTH
• Publiceringsår: 1996
• Språk: Engelska
• Sidor: 700-706
• Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
• Volym: 31
• Issue: 5
• Länkar: http://dx.doi.org/10.1109/4.509852
• Dokumenttyp: Artikel i tidskrift
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• Forskningsgrupp: Elektronikkonstruktion
• ISBN/ISSN/Övrigt: ISSN: 0018-9200