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An Integrated System-Level Design for Testability Methodology An Integrated System-Level Design for Testability Methodology

In English

Författare

Summary, in English

HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems.</p><p>The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design.</p><p>The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources.</p><p>Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system.</p><p>Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.

Publiceringsår

2000

Språk

Engelska

Dokumenttyp

Doktorsavhandling

Förlag

Linköping University Electronic Press

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • Digital systems
  • Test design
  • System-on-chip
  • Hardware
  • Systems

Status

Published

Handledare

  • Zebo Peng

ISBN/ISSN/Övrigt

  • ISBN: 91-7219-890-7

Försvarsdatum

19 december 2000

Försvarstid

13:15

Försvarsplats

Estraden, Hus E, Campus Valla, Linköpings universitet, Linköping

Opponent

  • [unknown unknown]